Multi-Rail Power Management Solutions for FPGA & MCU

Solutions for FPGA and DSP

Realizing Power Sequencing & High-Speed Transient Response without a PMIC

Field-Programmable Gate Arrays (FPGAs) are extremely common today in digital designs and many FPGA applications usually require multiple voltage rails to power them.  

Core voltage is normally 1.2V or 1.0V. DDR memory needs typically 1.5V or 1.8V and I/Os need 2.8V or 3.3V (refer to Fig.1 below):

 

(Fig.1: Power Configuration of Conventional FPGA & MCU)

 

Using a PMIC is today the most standard solution for providing the power to the multiple rails required by FPGAs. However, using a PMIC also has its own problems including how to make effective sequencing, probable unstable operation and EMI issues caused by long wiring from the PMIC to the FPGA as well as the influence of a common GND and finally, there are thermal considerations to be considered with a PMIC solution due to the concentration of heat in one place.

 

Power Sequencing

In addition to the specific power rails listed above, the different voltages must be powered on and perhaps more importantly, but often overlooked, powered off, in the correct order to maintain system stability. This is known as “power sequencing” and for start-up will usually begin with the Core voltage and, depending on the FPGA, will end with the I/O voltage. For power off the order is usually the opposite so I/O off first and Core voltage off last. Seems simple enough but there are pitfalls if it isn’t done properly and to do on/off sequencing properly usually means adding a large and expensive capacitor on the Core voltage rail to make sure that it stays on until all the other rails are powered off in the right order during power down.

 

Typical Power Sequencing Requirements

As mentioned, to have a secure shutdown sequence (power off), the 1.2V Core voltage should be maintained until all the other rails are off, so a large (>2,000µF) and expensive Capacitor is necessary for the Core rail. When the 5V rail is off, the UVLO of each secondary DC/DC operates and cuts off their outputs but the large capacitor of the Core rail is used to keep its voltage until all other rails are powered down.

Because of the large capacitor, it is also difficult to control the rise-up time of the Core rail to make the power on sequence and therefore it is quite common to have a Power Good (PG) output which is used to provide an Enable signal to next DC/DC in the sequence and so on (as shown in Fig.1).

Torex has a solution, however, that will enable the sequencing to be done without a PMIC and without the need for a large and expensive Capacitor on the Core voltage rail. Read on!

 

Point of Load method with Micro DC/DC (Integrated Coil) & Hi-SAT DC/DC

Point of Load (POL) with Torex XCL Micro DC/DCs and/or Hi-SAT COT solutions realize a very stable operation, fast transient response, good dispersion of heat and lower EMI thereby solving all the issues normally associated with powering FPGAs and power sequencing. The advantage of using individual ICs rather than a PMIC is that each IC can be located closer to each pin on the FPGA (POL).

Fig.2 shows a representation of a typical FPGA/MCU circuit schematic with a requirement for 3 power rails:

 

(Fig.2: Power Structure for FPGA & MCU with RESET IC)

 

The power sequence of start-up and shutdown of the 3 rails is important as already highlighted and it can actually be realized by a simple RC delay for the CE pins of each DC/DC (see Fig.6 & 7).

A RESET IC (Torex XC6126C) that monitors the VIN voltage is recommended for the ENABLE signal driving RC. Without the RESET IC, the sequence may be unreliable, or the VIN start-up waveform may be limited. Please note that if the primary side DC/DC has PG (Power Good) as shown in Fig.2, the ENABLE signal can be driven by the PG signal. In addition, it should also be noted that if the voltage from the output of the primary side DC/DC is 3.3V a line switch (such as the Torex XC8107) should be used instead of a Micro DC/DC or DC/DC.

 

Torex Power ICs suitable for use with FPGA & MCU

For stable FPGA and MCU operation, it is important that each DC/DC is positioned at the Point of Load as that reduces impedance between the DC/DC and the FPGA or MCU. It is equally important to separate each heat source and to layout the PCB to reduce EMI and to avoid interference between each power supply.

The XCL Micro DC/DC series with integrated coil is ideal for FPGA power supply use because they have low EMI, good thermal characteristics, are simple to design with and are very small (Fig.3 & 4)

(Fig.3: Pocket Style Micro DC/DC with Integrated Inductor for IOUTs up to 0.6A)

 

          (Fig.4: Multiple Style Micro DC/DC with Integrated Inductor for IOUTs >1A)  

 

 

Undershoot/Overshoot:
Recovery Time:

up to 4.5x Lower
up to 19x Faster

              (Fig.5: Load Transient Performance Comparison between Hi-SAT COT & Standard DC/DC)

 

Torex Solutions for FPGA & MCU (VIN=5.0V & VIN=3.3V)

With a 5.0V input, a 4.0V CMOS output RESET IC such as the Torex XC6126C40A7R-G is recommended to make the ENABLE signal whereas with a 3.3V input, a 2.4V solution is suitable, XC6126C24A7R-G. If the ENABLE is connected directly to VIN without a RESET IC, VIN must rise-up faster than the RC delays and the shutdown sequence will not be realised because each power IC will turn off when the VIN reaches the IC’s UVLO voltage.

If the primary DC/DC for 12/24V input has a PG pin, please use it for the ENABLE signal.
1/3 of the resistor value of the RC delay for the CE pins is suitable for the pull up resistor value of PG. For example, 22kΩ is good when VIN is 5.0V (Fig.6) and 15kΩ when VIN is 3.3V (Fig.7):

 

Internal Structure of the XCL214

 

Condition

VIN
ENABLE signal
Startup sequence
Shutdown sequence
: 5V
: "H" = 5V, "L", = 0V
: 1.0V→1.8V→3.3V
: 3.3V→1.8V→1.0V

 

Solution

3.3V 1.0A: XC9223B082DR-G
RD33=120kΩ, CD33=0.1μF, SD33=Schottky Diode

1.8V 1.0A: XC9223B082DR-G
RD18=64kΩ, CD18=0.1μF

1.0V 1.5A: XCL211B082DR
RD10=100kΩ, CD10=0.1μF, SD10=Schottky Diode

(Fig.6: Torex Solution for Powering FPGA/MCU when VIN=5.0V)

 

 

Internal Structure of the XCL214

 

Condition

VIN
ENABLE signal
Startup sequence
Shutdown sequence
: 3.3V
: "H" = 3.3V, "L", = 0V
: 1.0V→1.8V→3.3V
: 3.3V→1.8V→1.0V

 

Solution

3.3V 1.0A: XC8107AC10ER-G
RD33=64kΩ, CD33=0.1μF, SD33=Schottky Diode

1.8V 1.0A: XC9223B082DR-G
RD18=47kΩ, CD18=0.1μF

1.0V 1.5A: XCL211B082DR
RD10=100kΩ, CD10=0.1μF, SD10=Schottky Diode

(Fig.7: Torex Solution for Powering FPGA/MCU when VIN=3.3V)

 

 

In both cases (VIN=3.3V & VIN=5.0V), the power sequence can be realised using just a RC delay for each CE pin without the need for a dedicated PMIC, multiple RESET ICs or the large capacitor on the Core voltage rail highlighted earlier. A simpler solution with the added benefits of lower EMI and better thermal performance!

Samples and evaluation boards for all the Torex products mentioned in this feature are readily available. In addition, we can also provide solutions for the primary step-down DC/DC from 12V/24V so please ask your local Torex representative for details or give us a call directly.

 

For more information on the Torex products highlighted in this article please see:

XC9223 Series:
https://www.torex-europe.com/products/dc-dc-converters/step-down/xc9223/

XCL211 Series:
https://www.torex-europe.com/products/micro-dc-dc/step-down-1/xcl211/

XC6126 Series:
https://www.torex-europe.com/products/voltage-supervisors/low-power/xc6126/

XC8107 Series:
https://www.torex-europe.com/products/load-switches/xc8107/

 

For more information on our range of Micro DC/DC with integrated inductor please see:
https://www.torex-europe.com/microdcdc/